1. Field of the Invention
The invention relates generally to a clamp circuit and a boosting circuit using the same. More particularly, the invention relates to a clamp circuit and a boosting circuit using the same, capable of reducing read access time upon a data read operation of a memory cell in the semiconductor device, minimizing current loss and generating a stabilized word line voltage.
2. Description of the Prior Art
In the memory cell of EEPROM (electrically erasable and programmable read only memory), being a family of nonvolatile semiconductor memory devices, a program operation is performed by which electrons are accumulated at the floating gate electrode. A data read operation is performed by which variation in the threshold voltage (Vth) depending on whether the electrons exist or not is detected. A flash EEPROM (hereinafter called ‘flash memory device’) for performing the erase operation for data over the entire memory cell array and the erase operation for data in a block unit by dividing the memory cell array into given blocks is provided in the EEPROM.
Generally, the memory cell of the flash memory device may be classified into a stack gate type and a split gate type depending on its structure. For example, as shown in FIG. 9, the stack gate type memory cell includes a source region 904 and a drain region 906 formed at a semiconductor substrate 902, and a gate oxide film 908, a floating gate 910, a dielectric film 912 and a control gate 914, which are sequentially formed on the semiconductor substrate 902.
In the program operation of the stack gate type memory cell, as shown in Table 1 below and FIG. 10, a source voltage (Vs) and a bulk voltage (Vb), being a ground potential (0V), are applied to the source region 904 and the semiconductor substrate 902 (i.e., bulk), respectively, a gate voltage (Vg) of a positive high voltage (program voltage, +9V˜+10V) is applied to the control gate 914, a drain voltage (Vd) (for example, +5V˜+6V) is applied to the drain region 906, so that hot carriers are generated. In more detail, these hot carriers are generated since the electrons in the bulk are accumulated at the floating gate 910 by an electric field of the gate voltage (Vg) applied to the control gate 914 and electric charges supplied to the drain region 906 are thus accumulated. If the program operation is completed, the memory cells have a program threshold voltage of a target program voltage distribution (for example, 6V˜7V).
Meanwhile, in the erase operation of the stack gate type memory cell, as in Table 1 below, a negative high voltage (erase voltage, for example −9V˜−10V) is applied to the control gate 914 and the bulk voltage (Vb) (for example +5V˜+6V) is applied to the bulk, so that a F-N (Fowler-Nordheim) tunneling phenomenon is caused. The memory cells are erased in a sector unit sharing the bulk region. The electrons accumulated at the floating gate 908 are discharged toward the source region 904 by means of the F-N tunneling phenomenon, so that the memory cells have erase threshold voltages of given voltage distribution (far example, 1V˜3V).
The memory cells of which the threshold voltages are increased by the program operation are turned off since injection of current from the drain region 906 to the source region 904 is prevented upon the read operation. Further, the memory cells of which the threshold voltages are lowered by the erase operation are turned on since current is injected from the drain region 906 to the source region 904.
The flash memory cells are constructed to share the bulk region for higher integration in constructing the flash memory array. Accordingly, the flash memory cells contained in a single sector are erased at the same time. At this time, if all the flash memory cells in the sector are erased a,t the same time, there exist flash memory cells having the threshold voltages of below ‘0V’ (hereinafter called ‘over-erased memory cell’) among the flash memory cells due to uniformity against the threshold voltage of each of the flash memory cells. In order to compensate for this, a series of over-erase repair operations by which the threshold voltages of the over-erased flash memory cells are distributed into the erased threshold voltage distribution, are performed. This over-erase repair operation is performed by applying the gate voltage (Vg) (for example +3V) to the control gate 914, applying the drain voltage (Vd) (for example +5˜+6V) to the drain region 906 and making grounded the source region 904 and the bulk, as shown in Table 1 below.
TABLE 1DrainSourceOperatingGate VoltageVoltageVoltageBulk VoltageMode(Vg)(Vd)(Vs)(Vb)Program +9 V˜+10 V+5 V˜+6 V0 V0 VOperationErase−7 V˜−8 VFloatingFloating+8 V˜+9 VOperationOver-Erase+0 V+5 V˜+6 V0 V0 VCorrectionOperationRead +3.5˜+4.5 V+1 V0 V0 VOperation
As described above, in order for the program operation, the erase operation and the read operation of the flash memory device to operate, the function of the high-voltage generator for generating high voltages (for example, Vpgm (program voltage), Vera (erase voltage) and Vrea (read voltage)) supplied to the control gate of the memory cell is very important. Recently, as there is a trend that all the semiconductor memory devices are driven by a low voltage, it is also required that the flash memory devices be driven under an ultra low voltage (for example, below 2V or below 1.7V). On this trend, in order to maintain a rapid operating speed of the flash memory device, the function of the high-voltage generator is very important.
Of the high-voltage generators, in particular, the read voltage generator for generating the read operation voltage includes a bootstrap circuit for increasing the read operation speed. Such a bootstrap circuit boosts a low-potential power supply voltage over the voltage to supply the boosted voltage to the word line through the row decoder. In case where the low-potential power supply voltage is boosted using the bootstrap circuit, if the word line voltage boosted by the bootstrap circuit is too low, it is difficult to exactly read out current of the memory cell. If the word line voltage is too high, there is a problem in data retention characteristic since stress is applied to the control gate of the memory cell.
In the above, in order to solve the latter, a clamp circuit for dropping the voltage that is too high boosted (hereinafter called ‘boosting voltage’) by the bootstrap circuit down to a target voltage is positioned at the rear end of the bootstrap circuit. The mentioned clamp circuit will be described by reference to FIG. 11.
FIG. 11 is a block diagram of the boosting circuit in the common flash memory device.
Referring to FIG. 11, a boosting circuit 1100 includes a bootstrap circuit 1110, a reference voltage generator 1120 and a clamp circuit 1130. The bootstrap circuit 1110 receives a low-potential power supply voltage (LVcc) or a high-potential power supply voltage (HVcc) and boosts the voltage over the value of the voltage. The reference voltage generator 1120 is driven by an enable bar signal (ENb) being a synchronizing signal to output a reference voltage (Vref). The clamp circuit 1130 are driven by an enable signal (EN) and the enable bar signal (ENb) to compare the boosting voltage (Vboot) outputted from the bootstrap circuit 1110 and the reference voltage (Vref) outputted from the reference voltage generator 1120. As the result of the comparison, if the boosting voltage (Vboot) is higher than a target voltage, the clamp circuit 1130 drops the boosting voltage (Vboot) down to the target voltage and then outputs the final word line voltage (VBOOT).
However, such a boosting circuit 1100 includes one clamp circuit 1130 (that is, one clamp circuit that corresponds to one bootstrap circuit and is used to drop the boosting voltage (Vboot) outputted from one bootstrap circuit) in order to generate the word line voltage (VBOOT). Accordingly, access time (i.e., time taken to drop the boosting voltage down to the target voltage) taken to generate a stable word line voltage (VBOOT) is lengthened. Furthermore, in order to solve this problem, the word line voltage (VBOOT) is under shoot (see ‘A’ in FIG. 12) in case where a rapid access time is considered. Due to this, there occur many problems in stabilizing the semiconductor devices. In addition, there is a problem that read active current is not still controlled at the low-potential power supply voltage (LVcc) region wherein sensing is not performed at the clamping period.